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32 - channel, 14 - bit dac with full -s cale output voltage programmable from 50 v to 200 v data sheet ad5535b rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features high integration 32 - channel, 14 - bit dense dac? w ith integrated high voltage output amplifier guaranteed monotonic housed in 15 mm 15 mm csp_bga package full - scale output voltage p rogrammable from 50 v to 200 v via reference input 550 a drive capability integrated silicon diode for temperature monitoring dsp - /microcontroller - compatible serial interface 1.2 mhz channel update rate asynchronous reset facility C 10c to +85c temperature range applications optical microelectromechanical systems (mems) optical crosspoint switches micropositioning applications using piezoelectric actuators level setting in automotive test and measurement general descrip tion the ad5535b is a 32 - channel, 14 - bit dense dac? with an on - chip high voltage output amplifier. this device is targeted for optical micro - electromechanical systems. the output voltage range is programmable via the ref_in pin. the output range is 0 v to 50 v when ref_in = 1 v, and 0 v to 200 v when ref_in = 4 v. each amplifier can source 55 0 a, which is ideal for the deflection and control of optical mems mirrors. the selected digital - to - analo g converter ( dac ) register is written t o via the 3 - wire interface. the serial interface operates at clock rates of up to 30 mhz and is compatible with dsp and micro - controller interface standards. the device is operated with av cc = 4.75 v to 5.25 v, dv cc = 2.7 v to 5.25 v, v + = 4.75 v to 5.25 v, and v pp of up to 225 v. ref_in is buffered internally on the ad5535b and should be driven from a stable reference source. functional block dia gram figure 1. rf r1 rf r1 rf r1 rf r1 inter f ace contro l logic dac dac dac dac dv cc a v cc sync d in sclk dgnd agnd dac_gnd reset ref_in v pp pgnd v + 14-bit bus anode ca thode v out 0 v out 1 v out 30 v out 31 ad5535b 10852-001
ad5535b data sheet rev. a | page 2 of 16 t able of contents features ...................................................................................... 1 applications ............................................................................... 1 general description ................................................................. 1 functional block diagram ...................................................... 1 revision history ....................................................................... 2 specifications ............................................................................. 3 timing characteristics ........................................................ 5 absolute maximum ratings .................................................... 6 esd caution .......................................................................... 6 pin configuration and function descriptions ..................... 7 typical performance characteristics ..................................... 9 terminology ............................................................................ 11 functional description .......................................................... 12 dac section ........................................................................ 12 reset function .................................................................... 12 serial interfa ce .................................................................... 12 microprocessor interfacing ............................................... 12 applications ............................................................................. 14 mems mirror control application ................................. 14 ipc - 2221- compliant board layout ................................. 14 power supply d ecoupling recommendations ..................... 15 guidelines for printed circuit board layout ...................... 15 outline dimensions ............................................................... 16 ordering g uide ................................................................... 16 revision history 4/13 rev. 0 to rev. a change to general description section ......................................... 1 changes to dac section ................................................................ 12 changes to mems mirror control application section ........... 14 1/13 revision 0: initial versio n
data sheet ad5535b rev. a | page 3 of 16 specifications v pp = 215 v ; v + = 5 v; av cc = 5.25 v; dv cc = 2.7 v to 5.25 v; pgnd = agnd = dgnd = dac_gnd = 0 v; ref_in = 4.096 v; all outputs unloaded. all specifications t min to t max , unless otherwise noted. table 1 . parameter 1 k grade 2 unit test conditions/comments min typ max dc performance 3 resolution 14 bits integral nonlinearity (inl) 0.1 % of fsr differential nonlinearity (dnl) C 1 0.5 +1 lsb guaranteed monotonic zero code voltage 0.5 1 v output offset error C 1 +1 v offset drift 0.5 mv/c voltage gain 49 50 51 v/v gain temperature coefficient 5 ppm/c due to dac C 200 ppm/c due to dac and amplifier channel -to - channel gain match 4 C 5 +5 % output characteristics output voltage range 3 1 v pp ? 1 v output impedance 50 resistive load 4 , 5 1 m capacitive load 4 200 pf short - circuit current 0.55 ma dc crosstalk 4 3 4 lsb dc power supply rejection (psrr), v pp 70 db long - term drift 0.25 lsb outputs at midscale, measured over 30 days at 25c ac characteristics 4 settling time ? to ? scale step 60 s no load 60 s 200 pf load 1 lsb step 5 s no load 5 s 200 pf load slew rate 10 v/s no load 3 v/s 200 pf load C 3 db bandwidth 30 khz output noise spectral density 4.5 v/hz measured at 10 khz 0.1 hz to 10 hz output noise voltage 1 mv p -p digital -to - analog glitch impulse 1 lsb change around major carry positive transition 15 nv - s ec negative transition 8 nv - s ec analog crosstalk 2.5 v -s ec digital feedthrough 2 nv - s ec voltage reference, ref_in 6 av cc and v + must exceed ref_in by 1.15 v min imum input voltage range 4 1 4.096 v input impedance 60 k
ad5535b data sheet rev. a | page 4 of 16 parameter 1 k grade 2 unit test conditions/comments min typ max temperature measurement diode 4 peak inverse voltage, p iv 5 v cathode to anode forward diode drop, v f 0.65 0.8 v i f = 100 a, anode to cathode forward diode current, i f 100 a anode to cathode v f temperature coefficient, t c ?2.20 mv/c anode to cathode digital inputs 4 input current 5 10 a input low voltage 0.8 v input high voltage 2.0 v input hysteresis (sclk and sync only) 200 mv input capacitance 10 pf power supply voltages v pp ( 50 ref_in) + 1 225 v v + 4.75 5.25 v av cc 4.75 5.25 v dv cc 2.7 5.25 v power supply currents 7 i pp all c hannels at f ull - s cale 50 60 a/channel all c hannels at z ero - s cale 25 35 a/channel i + 1. 2 1. 7 ma ai cc 17.5 20 ma di cc 0.25 0.6 ma 1 see the terminology section. 2 k grade temperature range: ? 10c to +85c; typical = +25c. 3 linear output voltage range: 7 v to v pp ? 1 v. 4 guaranteed by design and characterization, not production tested. 5 e nsure that t j max is not exceeded. see the absolute maximum ratings section. 6 reference input determines output voltage range. using a 4.096 v reference ( ref198 ) gives an output voltage range of 2.5 0 v to 200 v. th e output range is programmable via the reference input. the full - scale output range is programmable from 50 v to 200 v. the linear output voltage range is restricted from 7 v to v pp ? 1 v. 7 outputs unloaded.
data sheet ad5535b rev. a | page 5 of 16 timing characteristi cs v pp = 210 v ; v + = +5 v; av cc = 5.25 v; dv cc = 2.7 v to 5.25 v; agnd = dgnd = dac_gnd = 0 v; ref_in = 4.096 v. all specifications t min to t max , unless otherwise noted. table 2 . parameter 1 , 2 , 3 a grade unit test conditions/comments f update 1.2 mhz max channel u pdate r ate f clkin 30 mhz max sclk f requency t 1 13 ns min sclk h igh p ulse w idth t 2 13 ns min sclk l ow p ulse wi dth t 3 15 ns min sync f alling e dge to sclk f alling e dge s etup t ime t 4 50 ns min sync l ow t ime t 5 10 ns min sync h igh t ime t 6 10 ns min d in s etup t ime t 7 5 ns min d in h old t ime t 8 200 ns min 19 th sclk f alling e dge to sync f alling e dge for n ext w rite t 9 20 ns min reset p ulse w idth 1 see figure 2 . 2 guaranteed by design and characterization, not production tested. 3 all input signals are specified with tr = tf = 5 ns (10% to 90% of dv cc ) and timed from a voltage level of (v il + v ih )/2 . figure 2. serial interface timing diagram 1 lsb 16 17 18 19 msb 1 reset 2 3 4 5 t 8 t 7 t 6 t 4 t 9 d in sync sclk t 5 t 3 t 2 t 1 10852-002
ad5535b data sheet rev. a | page 6 of 16 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating v pp to agnd 0.3 v to 24 0 v v + to agnd ?0.3 v to +7 v av cc to agnd, dac_gnd ?0.3 v to +7 v dv cc to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to dvcc + 0.3 v ref_in to agnd, dac_gnd ?0.3 v to avcc + 0.3 v v out 0 to v out 31 to agnd C 0.3 v to v pp + 0.3 v a node /c athode to agnd, dac_gnd ?0.3 v to +7 v agnd to dgnd ?0.3 v to +0.3 v operating temperature range industrial ?10c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 150c 124 - lead csp_bga package, ja thermal impedance 40c/w lead temperature jedec industry standard soldering j - std -020 esd human body model 2.5 kv machine model 250 v field induced charged device model 400 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. transient currents of up to 100 ma do not cause scr latch - up. esd caution
data sheet ad5535b rev. a | page 7 of 16 pin configuration an d function descripti ons figure 3 . pin configuration table 4 . pin assignments pin no. mnemonic a1 nc a2 v out 1 a4 v out 7 a6 v out 11 a8 v out 16 a10 v out 20 a12 v out 25 a14 nc b1 v out 0 b3 v out 4 b5 v out 9 b7 v out 13 b9 v out 17 b11 v out 21 b13 v out 26 c2 v out 3 c12 v out 22 c14 v out 29 d1 v out 2 d13 v out 23 e2 v out 5 e4 v out 8 e6 v out 12 e8 v out 15 e10 v out 19 e12 v out 24 e14 v out 31 f3 v out 6 f5 v out 10 f7 v out 14 f9 v out 18 f13 v out 30 g14 v out 28 pin no. mnemonic h1 v pp h2 v pp h4 to h11 agnd h13 v out 27 j3 to j12 agnd k1 v + k2 v + k3 to k14 agnd l1 nc l2 nc l3 to l13 agnd l14 dac_gnd m1 to m12 agnd m13 av cc m14 av cc n1 pgnd n2 pgnd n3 cathode n4 anode n5 to n14 agnd p1 nc p2 ref_in p3 dac_gnd p4 reset p5 dv cc p6 dgnd p7 test p8 d in p9 sclk p10 sync p11 to p13 agnd p14 nc a b c d e f g j h k l m n p 10 8 7 6 3 2 1 9 5 4 11 12 13 14 10 8 7 6 3 2 1 9 5 4 11 12 13 14 a b c d e f g j h k l m n p 10852-003
ad5535b data sheet rev. a | page 8 of 16 table 5 . pin function descriptions mnemonic description agnd analog gnd pins. av cc analog supply pins. voltage range from 4.75 v to 5.25 v. v pp output amplifier high voltage supply. volta ge range from (ref_in 50) + 1 v to 225 v. v + v + amplifier supply pins. voltage range from 4.75 v to 5.25 v. pgnd output amplifier ground reference pins. dgnd digital gnd pins. dv cc digital supply pins. voltage range from 2.7 v to 5.25 v. dac_gnd reference gnd supply for all dacs. ref_in reference voltage for channel 0 to channel 31. reference input range is 1 v to 4 v and can be used to program the full - scale output voltage from 50 v to 200 v. v out 0 to v out 31 analog output voltages from the 32 channels. anode anode of internal diode for diode temperature measurement. cathode cathode of internal diode for diode temperature measurement. sync active low input. this is the frame synchronization signal for the serial interface. while sync is low, data is transferred in upon the falling edge of sclk. sclk serial clock input. data is clocked into the shift register up on the falling edge of sclk. the pin operates at clock speeds of up to 30 mhz. internal pull - up device on logic input; theref ore, it can be left floating and defaults to a logic high condition. d in serial data input. data must be valid upon the falling edge of sclk. test f or normal operation , tie t his pin low . reset active low input. this pin can also be used to reset the complete device to its power - on reset conditions. zero code is loaded to the dacs. nc no c onnect. do not connect to these pins.
data sheet ad5535b rev. a | page 9 of 16 typical performance characteristics figure 4 . inte gral nonlinearity (inl) with full - scale ra nge = 50 v figure 5 . differential nonlinearity (dnl) with full - scale range = 50 v figure 6. i nl w ith full - scale range = 200 v figure 7. d nl with full - scale range = 200 v figure 8 . short - circuit current limit timing figure 9. worst - case adjacent channel crosstalk 16 ?16 0 input code inl error (lsb) 12 8 4 0 ?4 ?8 ?12 2048 4096 6144 8192 10240 12288 14336 16384 v pp = 60v v + = av cc = +5v ref_in = 1v t a = 25c 10852-018 1.00 ?1.00 0 input code dnl error (lsb) 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 2048 4096 6144 8192 10240 12288 14336 16384 v pp = 60v v + = av cc = +5v ref_in = 1v t a = 25c 10852-019 16 ?16 0 input code inl error (lsb) 12 8 4 0 ?4 ?8 ?12 2048 4096 6144 8192 10240 12288 14336 16384 v pp = 210v v + = av cc = +5.25v ref_in = 4.096v t a = 25 c 10852-020 1.00 ?1.00 0 input code dnl error (lsb) 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 2048 4096 6144 8192 10240 12288 14336 16384 v pp = 210v v + = av cc = +5.25v ref_in = 4.096v t a = 25 c 10852-021 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 0 2048 4096 6144 8192 10240 12288 14336 16384 input code dnl error (lsb) ch1 5v ch2 5v m 500ns ch1 21.6v t 10k ? dac amp channel 2 channel 1 channel 2 channel 1 10852-008 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 0 2048 4096 6144 8192 10240 12288 14336 16384 input code dnl error (lsb) ch1 50v ch2 200mv m 1 0s ch1 1 2 t v pp = 210v v + = av cc = +5.25v ref_in = 4.096v v out = 100v t a = 25c channel 1: channel output slew channel 2: ac crosstalk channel 2 area 11 v-sec 10852-009
ad5535b data sheet rev. a | page 10 of 16 figure 10 . output amplifier source and sink capability figure 11 . offset error vs. temperature figure 12 . gain error vs. temperature figure 13 . cumulative dc crosstalk effects on a single - channel output, switching all other channels in sequence figure 14 . settling time vs. capacitive load 0 ?5 2 source/sink current (ma) output voltage (v) 140 120 100 80 60 40 20 ?4 ?3 ?2 ?1 0 1 v pp = 210v v + = av cc = +5.25v ref_in = 4.096v v out = 70v t a = 25 c 10852-022 12.0 8.0 ?10 temperature (c) offset error (mv) 11.5 11.0 10.5 10.0 9.5 9.0 8.5 0 10 20 30 40 50 60 70 80 v pp = 210v v + = av cc = +5.25v ref_in = 4.096v 10852-028 ?1.0 ?1.5 ?10 temperature ( c) gain error (%) 0 10 20 30 40 50 60 70 80 ?1.1 ?1.2 ?1.3 ?1.4 v pp = 210v v + = av cc = +5.25v ref_in = 4.096v 10852-029 0.04 ?0.04 0 30 channel number dc crosstalk (v) 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 5 10 15 20 25 v pp = 210v v + = av cc = +5.25v ref_in = 4.096v t a = 25 c victim channel = 31 v out 31 = midscale full-scale transition on other channels in sequence. 10852-025 180 0 0 0.10 time (ms) output voltage (v) 160 140 120 100 80 60 40 20 0.02 0.04 0.06 0.08 0pf 100pf 200pf v pp = 210v v + = av cc = +5.25v ref_in = 4.096v t a = 25 c 1/4 full-scale to 3/4 full-scale step 10852-026
data sheet ad5535b rev. a | page 11 of 16 terminology integral nonlinearity (inl) a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is expressed as a percentage of full - s cale range. differential nonlinearity (dnl) the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified dnl of 1 lsb maximum ensures monotonicity. zero code voltage a measure of the output voltage present at the device output with all 0 s loaded to the dac. it includes the offset of the dac and the output amplifier and is expressed in v. offset error calculated by taking two points in the linear region of the transfer function, drawing a line through these points, and extrapolating back to the y - axis. it is expressed in v. voltage gain calculated from the change in output voltage for a change in code, multiplied by 16,384, and divided by the ref_in voltage. this is cal culated between two points in the linear section of the transfer function. gain error a measure of the output error with all 1s loaded to the dac, and the difference between the ideal and actual analog output range. ideally, the output should be 50 ref_i n. it is expressed as a percentage of full - scale range. dc power supply rejection ratio (psrr) a measure of the change in analog output for a change in v pp supply voltage. it is expressed in db, and v pp is varied 5%. dc crosstalk the dc change in the out put level of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) and the output change of all other dacs. it is expressed in lsb. output voltage settling time the time taken from when the last data bit is clocked i nto the dac until the output has settled to within 0.5 lsb of its final value. measured for a step change of ? to ? full scale. digital -to - analog glitch impulse the area of the glitch injected into the analog output when the code in the dac register chan ges state. it is specified as the area of the glitch in nv - s ec when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). analog crosstalk the area of the glitch transferred to t he output (v out ) of one dac due to a full - scale change in the output (v out ) of another dac. the area of the glitch is expressed in nv - s ec . digital feedthrough a measure of the impulse injected into the analog outputs from the digital control inputs when th e part is not being written to ( sync is high). it is specified in nv - s ec and measured with a worst - case change on the digital input pins, for example, from all 0s to all 1s and vice versa. output noise spectral density a measure of i nternally generated random noise. random noise is characterized as a spectral density (voltage per hz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in v/ hz.
ad5535b data sheet rev. a | page 12 of 16 functional description the ad5535b consists of a 32 - channel, 14 - bit dac with 200 v high voltage amplifiers in a single 15 mm 15 mm csp_bga package. the output voltage range is programmable via the ref_in pin. the output range is 0 v to 50 v when ref_in = 1 v, and 0 v to 200 v when ref_in = 4 v. communicat ion to the device is through a serial interface operating at clock rates of up to 30 mhz, which is compatible with dsp and microcontroller interface standards. a 5 - bit address and a 14 - bit data - word are loaded into the ad5535b input register via the serial interface. the channel address is decoded, and the data - word is converted into an analog output voltage for this channel. at power - on, all the dac registers are loaded with 0s. dac section the architecture of each dac channel consists of a resistor string dac, followed by an output buffer amplifier operating with a nominal gain of 50. the voltage at the ref_in pin provides the reference voltage for the corresponding dac. the input coding to the dac is straight binary, and the ideal dac output voltage is given by 14 _ 2 50 d v v in ref out = where d is the decimal equivalent (0 to 16,383) of the binary code, which is loaded to the dac register. the output buffer amplifier is specified to drive a load of 1 m? and 200 p f. the linear output voltage range for the output amplifier is from 7 v to v pp ? 1 v. the amplifier output bandwidth is typically 30 khz, and is capable of sourcing 55 0 a and sinking 2.8 ma. settling time for a ? to ? full - scale step change is typically 6 0 s with a load of up to 200 pf. reset function the reset function on the ad5535b can be used to reset all nodes on the device to their power - on reset condition. all the dacs are loaded with 0s, and all regist ers are cleared. t ake the reset pin low to implement the reset function . serial interface the serial interface is controlled by the three following pins: ? sync , which is the frame synchronization pin for the serial interface. ? sclk , which is the serial clock input that operates at clock speeds of up to 30 mhz. ? d in , which is the serial data input and d ata must be valid upon the falling edge of sclk. to update a single d ac channel, a 19 - bit data - word is written to the ad5535b input register. a4 to a0 bits the a4 to a0 bits can address any one of the 32 channels. a4 is the msb of the address , while a0 is the lsb. db13 to db0 bits the db13 to db0 bits are used to write a 14 - bit data - word into the addressed dac register. figure 2 is the timing diagram for a serial write to the ad5535b . the serial interface works with both a continuous and a discontinuous serial clock. the first falling edge of sync resets the serial clock counter to ensure that the correct numb er of bits are shifted into the serial shift register. any further edges on sync are ignored until the correct number of bits are shifted in. after 19 bits are shifted in, the sclk is ignored. for another serial transfer to take place, the counter must be reset by the falling edge of sync . the user must allow 200 ns (minimum) between successive writes. figure 15 . serial data format microprocessor inter facing ad5535b - to - adsp - bf527 interface the blackfin ? dsp is easily interfaced to the ad5535b without the need for extra logic. a data transfer is initiated by writing a word to the tx register after sport is enabled. in a write sequence, data is clocked out on each rising edge of the serial clock of the dsp and clocked into the ad5535b on the falling edge of its sclk. the sport can be configured to transmit 19 sclks while tfs is low. figure 16 shows the connection diagram. figure 16 . ad5535b - to - adsp - bf527 interface a4 a3 a2 a1 a0 db13 to db0 msb lsb 10852-010 10852-0 1 1 adsp-bf527 sync sport_tfs sclk sport_tsck sdin sport_dto gpio0 reset ad5535b
data sheet ad5535b rev. a | page 13 of 16 ad5535b - to - mc68hc11 interface the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock polarity bit (cpol) = 0, and clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr). sck of the mc68hc11 drives t he sclk of the ad5535b and the mosi output drives the serial data line (d in ) of the ad5535b . the sync signal is derived from a port line (pc7 ). when data is being transmitted to the ad5535b , the sync pin is ta ken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. the mc68hc11 transfers only eigh t bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. data is transmitted msb first. it is important to left justify the data in the spdr register so that the first 19 bits transmitted contain v alid data. pc7 must be pulled low to start a transfer. pc7 is then taken high and pulled low again before any further write cycles can take place. figure 17 shows the connection diagram. figure 17 . ad5535b - to - mc68hc11 interface ad5535b - to - pic16c6x/7x interface the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit = 0. this is done by writing to the synchronous serial port control register (sspcon) . in this example, i/o port ra1 is being used to pulse sync and to enable the serial port of the ad5535b . this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are nec essary to transmit 19 bits of data. data is transmitted msb first. it is important to left justify the data in the spdr register so that the first 19 bits transmitted contain valid data. ra1 must be pulled low to start a transfer. ra1 must then be brought high and pulled low again before any further write cycles can take place. figure 18 shows the connection diagram. figure 18 . ad5535b - to - pic16c6x/7x interface ad5535b - to - 8051 interface the ad5535b requires a clock synchronized to the serial dat a. t herefore, t he 8051 serial interface m ust operate in mode 0. in this mode, serial data exits the 8051 through r x d, and a shift clock is output on tx d. the sync signal is derived from a port line (p1.1). figure 19 shows how the 8051 is connected to the ad5535b . because the ad5535b shifts data out upon the rising edge of the shift clock and latches data in upon the falling edge, the shift clock must be inverted. note that the ad5535b also requires its data to be msb firs t. because the 8051 outputs lsb first, the transmit routine must take this into account. figure 19 . ad5535b - to - 8051 interface *additional pins omitted for clarity. ad5535b* mc68hc11* sclk d in sync sck mosi pc7 10852-012 *additional pins omitted for clarity. ad5535b* pic16c6x/7x* sclk d in sync sck/rc3 sdi/rc4 ra1 10852-013 *additional pins omitted for clarity. ad5535b* 8051* sclk d in sync txd rxd p1.1 10852-014
ad5535b data sheet rev. a | page 14 of 16 applications information mems mirror control application the ad5535b is targeted to all optical switching control systems based on mems technology. the ad5535b is a 32 - channel, 14- bit dac with integrated high voltage amplifiers. the output amplifiers are capable of generating an output range of 0 v to 200 v when using a 4 v reference. the full - scale output voltage is programmable from 50 v to 200 v using referen ce voltages from 1 v to 4 v. each amplifier can output 55 0 a and directly drives the control actuators, which determine the position of mems mirrors in optical switch applications. the ad5535b is generally us ed in a closed - loop feedback system , as shown in figure 20 , with a high resolution adc and dsp. the exact position of each mirror is measured using capac itive sensors. the sensor outputs are multiplexed using an adg739 4 - to - 1 multiplexer to an 8 - channel, 14 - bit adc ( ad7856 ). an alternative solution is to multiplex using a 32 - to - 1 multiplexer ( adg732 ) into a single - channel adc ( ad7671 ). the control loop is driven by an adsp - 21065l , a 32 - bit sharc? dsp with an spi - compatible sport interface. with 14 - bit monotonic behavior and a 0 v to 200 v output range, coupled with its fast serial interface, the ad5535b is ideally suited for controlli ng a cluster of mems - based mirrors. figure 20 . ad5535b in a mems - based optical switch ipc - 2 21- compliant board layo ut the diagram in figure 21 is a typical 2 - layer printed circuit board (pcb) layout for the ad5535b that complies with the specifications outlined in ipc - 221. do not connect to the four corner balls labeled as original no connects. connect b alls labeled as additional no connects to agnd. the routing shown in figure 21 shows the feasibility of connecting to the high voltage balls while complying with the spacing requirements of ipc - 221. figure 21 also shows the phys ical distances that are available. figure 21 . layout guidelines to comply with ipc - 221 adsp-21065l ad5535b output range 0v to 200v v out 0 14-bit dac 14-bit dac ref198 (4.096v) actuators for mems mirror array sensor + 4-to-1 mux (adg739) or 32-to-1 mux (adg732) 8-channel adc (ad7856) or single- channel adc (ad7671) +210v +5v v p p v + ref_in v out 31 10852-015 a b c d e f g j h k l m n p 10 8 7 6 3 2 1 9 5 4 11 12 13 14 1.414mm 2mm 250 m rad space = 405 m 100 m 250 m rad space = 405 m 250 m rad space = 433 m 100 m 250 m rad space = 433 m space = 433 m 100 m detail a a1 ball pad corner 1 1 1 original no connects additional no connects 1 10852-016
data sheet ad5535b rev. a | page 15 of 16 power supply decoupl ing recommendations on the ad5535b , it is recommended to tie all grounds together as close to the device as possible. if the number of supplies must be reduced, bring all supplies back separately and make a provision on the board via a lin k option to drive the av cc and v + pins from the same supply. decouple a ll power supp lies adequately with 10 f tantalum capacitors and 0.1 f ceramic capacitors. guidelines for p cb layout design p rinted circuit boards such that the analog and digital sect ions are separated and confined to the designated analog and digital sections of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally the best for ground planes because it optimizes shield ing of sensitive signal lines. join d igital and analog ground planes in one place only , at the agnd and dgnd pins of the high resolution converter. t o isolate the high frequency bus of the processor from the bus of the high resolution converters , buffer or latch d ata and address buses on the board . these act as a f araday shield and increase the signal - to - noise performance of the converters by reducing the amount of high frequency digital coupling. avoid running digital lines under the device because they couple noise onto the die. allow t he ground plane to run under the ic to avoid noise coupling. use as large a trace as possible for the supply lines of the device to provide low impedance paths and reduce the effects of glitches on the power supply line. shield c omponents, such as clocks with fast - switching signals, with digital ground to avoid radiating noise to other sections of the board. n ever run clock signals near the analog inputs of the device. avoid crossovers of digital and analog signals. keep t races for analog inputs as wide and short as possible and shield with analog ground if possible. run t races on opposite sides of the 2 - layer pcb at right angles to each other to reduce the effects of feedthrough through the board. a microstrip technique i s by far the best, but it is not always possible to use with a double - sided board. in this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. multilayer printed circuit boards with dedicated ground, power, and tracking layers offer the optimum solution in terms of obtaining analog performance, but at increased manufacturing costs. good decoupling is vitally important when using high resolu - tion converters. decouple a ll analog supplies with 10 f tantalum capacitors in parallel with 0.1 f ceramic capacitors to analog ground. to achieve the best results from the decoupling components , place them as close to the device as possible, ideally right up against the ic or the ic socket. the main aim of a bypassing element is to maximize the charge stored in the bypass loop while simultaneously minimizing the inductance of this loop. inductance in the loo p acts as an impedance to high frequency transients and results in power supply spiking. by keeping the decoupling as close to the device as possible, the loop area is kept as small as possible, thereby reducing the possibility of power supply spikes. d eco uple d igital supplies of high resolution converters with 10 f tantalum capacitors and 0.1 f ceramic capacitors to the digital ground plane. decouple t he v + suppl y with a 10 f tantalum capacitor and a 0.1 f ceramic capacitor to agnd. decouple a ll logic chips with 0.1 f ceramic capacitors to digital ground to decouple high frequency effects associated with digital circuitry.
ad5535b data sheet rev. a | page 16 of 16 outline dimensions figure 22 . 124 - lead chip scale package ball grid array [csp_bga] (bc - 124 - 2) dimensions shown in millimeters ordering guide model 1 function output voltage span temperature range package description package option ad5 5 35bkbc 32 dacs 0 v to 200 v maximum ?10c to +85c 124 - lead csp_bga bc - 124 -2 ad5 5 35bkbcz 32 dacs 0 v to 200 v maximum ?10c to +85c 124 - lead csp_bga bc - 124 -2 eval - ad55 3 5bebz evaluation board 1 z = rohs compliant part. detail a ball diameter a b c d e f g j h k l m n p 10 8 7 6 3 2 1 9 5 4 11 12 13 14 * 1.25 max 0.85 min * 0.41 0.36 0.31 * 0.46 nom * compliant with jedec standards mo-192-aae-1 with exception to dimensions indicated by an asterisk. nominal ball size is reduced from 0.60mm to 0.46mm. a1 ball corner top view detail a bottom view seating plane coplanarity 0.12 13.00 ref 12-19-2012- a 15.10 15.00 sq 14.90 ball a1 pad corner 1.00 bsc 1.70 max ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10852 - 0 - 4/13(a)

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